Memory control apparatus and memory control method

A memory control apparatus controlling access to memory, comprising:

• buffer memory for temporarily storing data stored in the memory;
• an instruction reception unit for receiving an instruction to the memory;
• a buffer memory security-dedicated use packet transmission unit for transmitting a buffer memory security-dedicated use packet for securing a capacity of memory in the buffer memory that is required by an instruction on the basis of the instruction received by the instruction reception unit;
• a buffer memory validation signal reception unit for receiving a buffer memory validation signal corresponding to the buffer memory security-dedicated use packet transmitted by the buffer memory security-dedicated use packet transmission unit;
• and
• an instruction execution unit for executing the instruction received by the instruction reception unit on the basis of the buffer memory validation signal received by the buffer memory validation signal reception unit.