Method, system, and computer program product for mapping a logical design onto an integrated circuit with slack apportionment

A system for mapping a logical design including multiple logical blocks onto an integrated circuit chip, comprising:

• an input for receiving the logical design;
• a processor for creating a chip level floor plan including temporary areas on the chip set aside for accommodating logical blocks having logical content including timing requirements based on the logical design, translating the temporary areas into physical cells on the chip with pins assigned for inputs and outputs for the logical blocks, mapping the logical blocks to the physical cells on the chip in a time sensitive manner using timing assertions to form temporary logical partitions, wherein the timing assertions include the timing requirements of the logical blocks, connecting blocks on the chip, including the temporary logical, partitions, based on the timing assertions, performing a timing analysis on the chip to determine timing slack associated with each temporary logical partition, determining whether the timing slack associated with each, temporary logical partition is acceptable, and, if the timing slack associated with each temporary logical partition is not acceptable, apportioning for the slack in the temporary logical partitions and feeding back apportioned slack information in the form of timing assertions for use in mapping the logical blocks to the physical cells, wherein the processor repeats the mapping, connecting, timing analysis, and apportioning for slack until the timing slack associated with each temporary logical partition is determined to be acceptable.

A computer program product for mapping a logical design including multiple logical blocks onto an integrated circuit chip, comprising a computer usable medium having a computer readable program, wherein the computer readable program, when executed on a computer, causes the computer to perform steps including:

• creating a chip level floor plan including temporary areas on the chip set aside for accommodating logical blocks having logical content including timing requirements based on the logical design;
• translating the temporary areas into physical cells on the chip with pins assigned for inputs and outputs for the logical blocks;
• mapping the logical blocks to the physical cells on the chip in a time sensitive manner using timing assertions to form temporary logical partitions, wherein the timing assertions include the timing requirements of the logical blocks;
• connecting blocks on the chip, including the temporary logical partitions, based on the timing assertions;
• performing a timing analysis on the chip to determine timing slack associated with each temporary logical partition;
• determining whether the timing slack associated with each temporary logical partition is acceptable;
• and
• if the timing slack associated with each temporary logical partition is not acceptable, apportioning for the slack in the temporary logical partitions and feeding back apportioned slack information in the form of timing assertions for use in mapping the logical blocks to the physical cells, wherein the steps of mapping, connecting, performing a timing analysis, and apportioning for slack are repeated until the tuning slack associated with each temporary logical partition is determined to be acceptable.