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US 2008/0307293 A1Published application
Computational efficient convolutional coding with rate matching
AssigneeTelefonaktiebolaget L M Ericsson (publ)
InventorJung-Fu Thomas Cheng
Life of this patent
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Abstract
An error coding circuit comprises a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits, an interleaver circuit for interleaving parity bits within each group of parity bits, and a rate-matching circuit for outputting a selected number of the interleaved parity bits ordered by group to obtain a desired code rate.
Claims20
An error coding circuit comprising:
- a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits;
- an interleaver circuit for interleaving parity bits within each group of parity bits;
- and
- a rate-matching circuit for outputting a selected number of said interleaved parity bits ordered by group to obtain a desired code rate.
1 more element
A method for error coding an input bit stream, said method comprising:
- coding said input bit stream in a non-systematic convolutional encoder to produce two or more groups of parity bits;
- interleaving parity bits within each group of parity bits;
- and
- outputting a selected number of said interleaved parity bits ordered by group to obtain a desired code rate.
1 more element
Dependencies are inferred from the claim text.