Scan cells with minimized shoot-through and scan chains and integrated circuits using the same

A scan cell comprising:

• a data input and a shift input;
• input selection circuitry for selecting between the data and shift inputs during normal, capture, and shift modes in response to only a first control signal and a second control signal, comprising:
• a first storage element for storing a bit representing a state of the first control signal in response to a change in state of the second control signals;
• and
• multiplexing circuitry operable to:
• in the normal mode, select the data input in response to a first state of the second control signal;
• in the capture mode, select the data input when the bit stored in the first storage element represents a first state of the first control signal;
• and
• in the shift mode, select the shift input when the bit stored in the first storage element represents a second state of the first control signal;
• and
• a second storage element for storing, in response to the first state of the first control signal, data presented at the selected one of the data and shift inputs.

A method of operating a scan cell comprising:

• selecting between a data input and a shift input during normal, capture, and shift modes in response to only two control signals, comprising:
• storing in a first storage element a bit representing a state of a first one of the two control signals in response to a change in state of a second one of the two control signals;
• and
• in the normal mode, selecting the data input in response to a first state of the second one of the two control signals;
• in the capture mode, selecting the data input when the stored bit stored in the first storage element represents a first state of the first of the two control signals;
• and
• in the shift mode, selecting the shift input when the stored bit stored in the first storage element represents a second state of the first of the two control signals;
• and
• storing in a second storage element, in response to the first state of the first one of the two control signals, data presented at the selected one of the data and shift inputs.

An integrated circuit comprising:

• a scan chain including a plurality of scan cells, at least one of the scan cells operating in one of normal, capture, and shift modes selected in response to only a clock signal and a scan enable signal, the at least one of the scan cells comprising:
• a data input and a shift input;
• a flip-flop for storing a bit representing a state of the clock signal at an edge of the scan enable signal;
• selector circuitry for selecting between the data input and the shift input in response to the bit stored in the flip-flop, the selector circuitry operable to:
• in the normal mode, select the data input in response to a first state of the scan enable signal;
• in the capture mode, selecting the data input in response to a bit stored in the first storage element which represents a first state of the clock signal at the edge of the scan enable signal;
• and
• in the shift mode, selecting the shift input in response to a bit stored in the first storage element which represents a second state of the clock signal control at the edge of the scan enable signal;
• a register for storing in response to the first state of the clock signal data presented at the selected one of the data and shift inputs.