Memory apparatus and method and reduced pin count apparatus and method

A reduced-pin-count device, comprising:

• an output verifier used to receive a plurality of outputs of a memory device under test and to compare whether the outputs are identical, sending a pass signal if the outputs are identical and sending a failure signal if at least one of the outputs is different;
• and
• a counter used to output an error indication signal to indicate an output address of an erroneous data in the memory device under test if the output verifier sends the failure signal.

A reduced-pin-count method, comprising:

• verifying whether a plurality of outputs of a memory device under test are identical, sending a pass signal if the outputs are identical and sending a failure signal if at least one of the outputs is different;
• and
• sending an error indication signal to indicate an output address of an erroneous data in the memory device under test if the failure signal is sent.