Power management electronic circuits, systems, and methods and processes of manufacture

An electronic device comprising

• a processor;
• and
• a power management circuit operable to establish a selected operating point including a voltage and operating frequency for said processor thereby defining ranges bounded by adjacent pairs of operating frequencies,
• said processor operable to generate a target frequency and operable to determine whether or not the target frequency is outside or within a current range and further operable to configure an operating point transition in said power management circuit when the target frequency is outside the current range.

An electronic circuit comprising:

• a processor;
• a functional circuit coupled to said processor;
• a power management register circuit coupled to said processor for holding configuration bits in said power management register circuit;
• a power management control circuit coupled to said power management register circuit and said power management control circuit operable in response to the configuration bits for voltage and frequency scaling combined with conditional dynamic power switching of said processor.

An electronic circuit comprising:

• a processor operable to run an application;
• a memory coupled to said processor;
• a peripheral including a buffer coupled to said memory and said buffer having a buffer state output;
• and
• a power management control circuit coupled to said processor, to said memory and to said buffer state output, said power management control circuit conditionally operable in a dynamic power switching mode having a controlled sequence wherein said processor runs the application and delivers resulting information to said memory, and power to said processor is substantially lowered, and portions of the resulting information are successively transferred from said memory to said buffer depending on the buffer state output, and then power to said processor is restored.

An electronic circuit comprising:

• a power-managed processing circuit operable to execute an application context and said power-managed processing circuit subject to active power consumption when an application is running and static power consumption if its power is on when the application is not running;
• a dynamic voltage and frequency scaling (DVFS) circuit operable to establish a voltage and a clock frequency for said power-managed circuit;
• and
• a dynamic power switching (DPS) circuit coupled to said dynamic voltage and frequency scaling circuit, said DPS circuit operable to determine an excess of the clock frequency over a target frequency for said power-managed processing circuit, and when that excess exceeds a predetermined threshold to initiate a context save by said power-managed processing circuit then temporarily substantially reduce the static power consumption.

An electronic system comprising:

• a first integrated circuit including
• a processor;
• a functional circuit coupled to said processor;
• a power management register circuit coupled to said processor to hold configuration bits;
• a power management control circuit coupled to said power management register circuit and said power management control circuit operable in response to the configuration bits for combined voltage and frequency scaling and conditional dynamic power switching of said processor;
• and
• a second integrated circuit including
• a power controller coupled to said power management control circuit of said first integrated circuit;
• and
• a first controllable voltage power supply responsive to said power controller and said first controllable voltage power supply coupled to supply a controllable voltage to power said processor;
• and
• a second controllable voltage power supply responsive to said power controller and said second controllable voltage power supply coupled to supply a controllable voltage to power said functional circuit said first integrated circuit.

An electronic camera system comprising:

• a camera sensor operable for successive capture operations to capture image frames;
• a digital signal processor operable for image processing;
• an interconnect coupled to said digital signal processor;
• an interconnect clock coupled to said interconnect;
• a power management control circuit;
• a camera interface coupled to said camera sensor and to said interconnect, said camera interface including a buffer and supporting a smart standby mode wherein when said camera sensor is enabled, a time interval elapses between the successive capture operations, said camera interface operable during the time interval to assert a camera standby signal to the power management control circuit that said camera interface is not accessing said interconnect, said power management control circuit operable during the time interval to shut down said interconnect clock and assert a wait signal to prevent sourcing by said digital signal processor onto said interconnect;
• and at substantially the end of the time interval the camera interface further operable to de-assert the camera standby signal to indicate that said camera interface is ready to access said interconnect, and said power management control circuit operable to then disable the wait signal and activate said interconnect clock;
• and
• a display coupled to said digital signal processor.

A mobile video electronic system comprising:

• a processor;
• a power management control circuit coupled to said processor and operable for voltage and frequency scaling combined with conditional dynamic power switching of said processor;
• a video camera coupled to said processor and to said power management control circuit;
• a modem coupled to said power management control circuit;
• and
• a video display operable to display video content and coupled to said power management control circuit.