Data exchange and communication between execution units in a parallel processor

An integrated-circuit processing device comprising:

• a plurality of execution lanes to execute instructions in parallel;
• an interlane switch coupled to the execution lanes to enable data to be exchanged between respective pairs of the execution lanes;
• an instruction sequencing circuit to receive an instruction to enable data exchange between the execution lanes;
• and
• a control circuit to examine, in response to the instruction, respective requests from the execution lanes to determine a set of the execution lanes that may send data to one or more others of the execution lanes during a first interval, the control circuit to signal each execution lane within the set of the execution lanes to indicate that the execution lane may send data to the one or others of the execution lanes.

A manufacture, including a computer-readable media having information embodied therein that includes a description of an integrated circuit (IC) package, the information including descriptions of:

• a plurality of execution lanes to execute instructions in parallel;
• an interlane switch coupled to the execution lanes to enable data to be exchanged between respective pairs of the execution lanes;
• an instruction sequencing circuit to receive an instruction to enable exchange of data between the execution lanes;
• and
• a control circuit to examine, in response to the instruction, respective requests from the execution lanes to determine a set of the execution lanes that may send data to one or more others of the execution lanes during a first interval, the control circuit to signal each execution lane within the set of the execution lanes to indicate that the execution lane may send data to the one or others of the execution lanes.