Method and apparatus to efficiently evaluate monotonicity

A processor architecture used in digital signal processing to efficiently analyze monotonicity of a set of N input values, the processor architecture comprising:

• a comparison logic circuit configured to compare the set of N input values and generate N comparison signals, each of the N comparison signals indicating a higher value of two different input values from the set of N input values;
• a calculation circuit coupled to the comparison logic circuit and configured to calculate N absolute differences of the two different input values;
• a set of N comparators coupled to the calculation circuit configured to determine which of the N absolute differences are greater than a reference value, each of the set of N comparators further configured to generate a second comparison signal indicating whether a absolute difference is greater than the reference value;
• a plurality of logic elements coupled to the set of N comparators and configured to check a plurality of cases of monotonicity, each logic element of the plurality of logic elements configured to determine a unique case of monotonicity using one of the N comparison signals and the second comparison signal and generating a control signal, the control signal indicating whether the unique case of monotonicity of the plurality of cases of monotonicity is valid;
• and
• a selection unit coupled to the plurality of logic elements and configured to select a monotonicity output value.

A method of determining monotonicity of a set of N input values, the method comprising:

• pairwise comparing the set of N input values to determine a higher value of two different input values from the set of N input values;
• calculating N absolute differences of the two different input values;
• determining which of the N absolute differences are greater than a given reference value;
• checking a plurality of cases of monotonicity, the checking performed using a set of monotonicity conditions evaluated with a result of the step of pairwise comparing and the step of determining which of the N absolute differences are greater, the checking generating control signals indicating which case of monotonicity of the plurality of cases of monotonicity is valid;
• and
• using the generated control signals to select a monotonicity output value from a set of output values, the monotonicity output value being a result of a monotonicity instruction.