Loading test data into execution units in a graphics card to test the execution units

A system, comprising:

• a bus;
• a cache coupled to the bus including instructions;
• multiple execution units each including an instruction queue, wherein the execution units are coupled to the bus;
• a design test unit enabled to cause operations to:
• load test instructions into the cache during a design test mode;
• cause the transfer of cache instructions comprising the loaded test instructions concurrently to the instruction queue of each execution unit to concurrently load the cache instructions into the instruction queues of the execution units;
• and
• cause the execution units to concurrently execute the cache instructions to fetch test instructions from the cache to load into memories of the execution units and execute during the design test mode.