US 2008/0307193 A1 · Semiconductor integrated circuit

Abstract

A semiconductor integrated circuit (chip) includes a primary TAP controller and a secondary TAP controller. The primary TAP controller interprets a bit string of n bits included in the group 1 having an m-bit length (m≧2) and less than the total number of m bits as an instruction that carries out a processing for a control object and interprets each bit string having an m-bit length as an instruction that carries out no processing for the control object. The m-bit length is obtained by adding a predetermined single bit string to each bit string included in the group 1 consisting of at least two or more bit strings having an n-bit length, respectively. The secondary TAP controller extracts a single bit string denoting an instruction that has an n-bit length and carries out no processing for the control object from each bit string interpreted by the primary TAP controller as an instruction that carries out a processing for the control object, then interprets the single bit string.

Claims14

Dependent claims

A semiconductor integrated circuit, comprising:

a functional block performing a predetermined operation thereof;
another functional block performing a predetermined operation thereof;
a controller interpreting each of first bit sequences to carry out processing for said function block and interpreting each of second bit sequences not to carry out processing for said functional block, each of said first bit sequences being a member of a first bit sequence group including a plurality of bit sequences having a first bit length, each of said second bit sequences consisting of one of third bit sequences and a particular bit sequence, each of said second bit sequences being a member of said first bit sequence group, each of said third bit sequences being a member of a second bit sequence group including a plurality of bit sequences having a second bit length shorter than said first bit length;
and
another controller interpreting each of said third bit sequences and interpreting a part of one of said first bit sequences as one of said third bit sequences not to carry out processing for said another functional block.

2 more elements

A semiconductor integrated circuit, comprising:

an input port receiving an instruction code and another instruction code;
a debug controller coupled to said input port to receive said instruction code and said another instruction code via said input port;
another debug controller coupled to said input port to receive said instruction code and said another instruction code via said input port, said instruction code being inputted into said input port for operating said debug controller, said another instruction code being inputted into said input port for operating said another debug controller;
a functional block performing a predetermined function and debugged by said debug controller;
and
another functional block performing a predetermined function and debugged by said another debug controller, wherein
said debug controller controls said functional block in response to receiving said instruction code and does not control said another functional block when said debug controller receives said another instruction code, wherein
said another debug controller controls said another functional block in response to receiving said another instruction code and does not control said another functional block when said another debug controller receives said instruction code, wherein
said instruction code is a first bit sequence having a first bit length and said another instruction code is a second bit sequence having a second bit length shorter than said first bit length. wherein
said debug controller interprets said first bit sequence as said instruction code in order to control said functional block, and interprets a third bit sequence consisting of said second bit sequence and a particular bit sequence in order not to control said functional block when said controller receives said second bit sequence as said another instruction code, said third bit sequence having said first bit length.

7 more elements

Dependencies are inferred from the claim text.

Semiconductor integrated circuit

Life of this patent

Semiconductor integrated circuit

Life of this patent

Abstract

Claims14