Store Handling in a Processor
AssigneeApple Inc.
InventorsRamesh Gunna, Po-Yung Chang, Sudarshan Kadambi
Life of this patent
Estimating the term…
Abstract
In one embodiment, a processor may be configured to write ECC granular stores into the data cache, while non-ECC granular stores may be merged with cache data in a memory request buffer. In one embodiment, a processor may be configured to detect that a victim block writeback hits one or more stores in a memory request buffer (or vice versa) and may convert the victim block writeback to a fill. In one embodiment, a processor may speculatively issue stores that are subsequent to a load from a load/store queue, but prevent the update for the stores in response to a snoop hit on the load.
Claims21
A processor comprising:
- a load/store unit comprising a queue, wherein the load/store unit is configured to issue a store memory operation from the queue;
- a data cache coupled to the load/store unit;
- a memory request buffer coupled to the load/store unit;
- and
- a control unit configured to cause the issued store memory operation to write the data cache responsive to the issued store memory operation only updating one or more complete error correction code (ECC) granules, and wherein the control unit is configured to cause the issued store memory operation to be written to the memory request buffer responsive to the issued store operation partially updating at least one ECC granule.
A method comprising:
- issuing a store memory operation from a queue;
- writing a data cache responsive to the issued store memory operation only updating one or more complete error correction code (ECC) granules;
- and
- writing the issued store memory operation to a memory request buffer responsive to the issued store operation partially updating at least one ECC granule.
A processor comprising:
- a pipeline comprising one or more stages between a load/store unit and one or more target locations of one or more store memory operations;
- and
- the load store unit coupled to the pipeline, wherein the load/store unit comprises a load/store queue having an entry allocated to each pending load/store memory operation, wherein the load/store queue is coupled to receive a snoop address indicating a cache block that is to be updated by another device in a system with the processor, and wherein, responsive to detecting that the snoop address hits a load memory operation in the load/store queue and identifying a subsequent store memory operation in the load/store buffer that has been issued to the pipeline, the load/store unit is configured to prevent an update for the subsequent store memory operation in the pipeline at the target location of the subsequent store memory operation.
A method comprising:
- receiving, in a processor, a snoop address indicating a cache block that is to be updated by another device in a system with the processor;
- detecting that the snoop address hits a load memory operation in a load/store queue;
- identifying a subsequent store memory operation in the load/store queue that has been issued to a pipeline between a load/store unit that includes the load/store queue and one or more target locations of one or more store memory operations;
- and
- preventing an update for the subsequent store memory operation in the pipeline at the target location of the subsequent store memory operation responsive to the detecting and the identifying.
Dependencies are inferred from the claim text.