System and Method for Dual-Ported I2C Flash Memory

A system, comprising:

• a flash memory array configured to couple to an I2C bus;
• a first I2C port coupled to the flash memory array, comprising a first pair of I2C wires and a hardware I2C engine coupled to the first pair of I2C wires and configured in a first addressing protocol;
• a second I2C port coupled to the flash memory array, comprising a second pair of I2C wires and a software I2C engine coupled to the second pair of wires and configured in a second addressing protocol, differing from the first addressing protocol;
• and
• wherein the first I2C port interfaces with the flash memory array as a single array;
• wherein the second I2C port interfaces with the flash memory array as two independent arrays;
• and
• wherein the first I2C port and the second I2C port are accessible to the I2C bus.

An apparatus comprising a computer program product for emulating a dual-port I2C device, the computer program product having a tangible computer-readable medium with a computer program embodied thereon, the computer program comprising:

• computer code for receiving a transmit package for transmission on an Ethernet network;
• computer code for monitoring a bus for I2C traffic;
• computer code for receiving an I2C interrupt on the bus;
• computer code for determining whether the received I2C interrupt is one of either a hardware interrupt or a software interrupt;
• computer code for, in the event the received I2C interrupt is a hardware interrupt, responding to the hardware interrupt, and accessing a flash memory for read/write operation based on the hardware interrupt;
• and
• computer code for, in the event the received I2C interrupt is a software interrupt responding to the software interrupt, and accessing a flash memory for read/write operation based on the software interrupt.