Computer system bus bridge

8) A bus bridge in a computer processor system that provides conversion between an a Giga-Processor Ultralite (GPUL) bus and an interface bus comprising:

• a GPUL to interface bus command and data conversion unit comprising:
• a read buffer assign counter and a write buffer assign counter;
• command and tag conversion logic to convert commands and tags from the GPUL bus to the interface bus;
• a read command counter, a write command counter and a credit counter;
• logic for the read command counter, the write command counter and the credit counters to signal to the GPUL bus that a read command, a write command or a credit is available;
• a plurality of read intervention buffers that capture data from the GPUL bus when a transaction tag match is made between a transaction coming in on the GPUL bus and the transaction tag, wherein the plurality of read intervention buffers comprise an array of registers for each buffer with a load address generator circuit to hold an address to access the array of registers;
• a snoop ticket order counter that assigns a number to the plurality of read intervention buffers to maintain a first-in-first-out order;
• an interface bus to GPUL command and data conversion unit comprising:
• an array of read buffers;
• command and tag conversion logic to convert commands and tags from the interface bus to the GPUL bus;
• and
• a snoop response unit with snoop response conversion logic and a read command counter.

9) A computer processor system comprising:

• at least one processor with a Giga-Processor Ultralite (GPUL) bus;
• a transceiver with a bridge;
• an interface bus,
• wherein the bridge further comprises:
• an GPUL to interface bus command and data conversion unit;
• an interface bus to GPUL command and data conversion unit;
• and
• a snoop response unit that provides a transaction tag for a transaction on the GPUL bus;
• wherein the bridge provides a conversion between the GPUL bus and the output bus, and
• wherein the GPUL to interface bus command and data conversion unit further comprises:
• a plurality of read intervention buffers that capture data from the GPUL bus when a transaction tag match is made between a transaction coming in on the GPUL bus and the transaction tag, wherein the plurality of read intervention buffers comprise an array of registers for each buffer with a load address generator circuit to hold an address to access the array of registers;
• a read buffer assign counter that determines which of the plurality of read intervention buffers is used to store a transaction;
• a snoop ticket order counter that assigns a number to the plurality of read intervention buffers to maintain a first-in-first-out order.