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OwnerRonald E. Freking, Philip R. Hillier, III +1inventors
InventorsRONALD E. FREKING, Philip R. Hillier, III, Curtis C. Wollbrink
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A method, computer system, and PCI Express device/protocol for a design structure that enables high performance IO data transfers for multiple, different IO configurations, which include variable packet sizes and/or variable/different numbers of transactions on the IO link. PCI Express protocol is enhanced to support utilization of counters and dynamically variable queue sizes. In addition to the standard queue entries, several (or a selected number of) dynamically changeable queue entries are provided/reserved and a dynamic queue modification (DQM) utility is provided within the enhanced PCI Express protocol to monitor ongoing, current data transfer and manage when the size(s) of the queue entries are modified (increased or decreased) based on current data traffic transmitting on the PCI Express IO link. The enhanced PCI Express protocol provides an equilibrium point at which many large data packets are transferred efficiently, while imposing a limit on the number of each size of packets outstanding.
A design structure embodied in a computer readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
A method in a computer-aided design system for generating a functional design model of a PCI express bus controller having one or more PCI queues with one or more queue entries and a dynamic queue modification (DQM) logic, said method comprising:
Dependencies are inferred from the claim text.