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OwnerYi-Feng Jang, Zhi-Jian Liang +2inventors
InventorsYi-Feng Jang, Zhi-Jian Liang, Hai-Ping Liu, Hai-Jun Shu
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A chip with a high performance programmable logic system interface, including a first internal device, a second internal device and a bus master, is provided. The first internal device, which is integrated into the chip, communicates with an external device by a first set of internal buses and a first set of external buses. The second internal device, which is integrated into the chip, communicates with the external device by a second set of internal buses and a second set of external buses. The bus master is configured to control the first set of internal buses, the first set of external buses, the second set of internal buses and the second set of external buses. The first internal device and the second internal device communicate with the bus master simultaneously.
A chip with high performance programmable logic system interface including a first internal device received in the chip and communicating with an external device by means of a first set of internal bus and a first set of external bus;
A high performance programmable logic system interface contained in a chip, the chip including a first internal device, a second internal device, and a master bus;
Dependencies are inferred from the claim text.