Generation of test cases with range constraints for floating point add and subtract instructions

A design verification system for a floating point computation unit, comprising a processor adapted to execute:

• a generator that receives a definition of a floating point operation to test, said definition comprising a first floating point operand having a first floating point input interval and a second floating point operand having a second floating point input interval, and a floating point result having a floating point output interval, said first and second floating point input intervals and said floating point output interval having respective upper and lower floating point limits, said generator operative to perform the steps of:
• defining a first reduced interval for said first floating point operand responsively to said upper and lower floating point limits of said second floating point input interval and said floating point output interval;
• selecting a first machine number in said first floating point input interval;
• defining a second reduced interval for said second floating point operand responsively to said first machine number and to said upper and lower limits of said floating point output interval;
• selecting a second machine number in said second reduced interval;
• and
• an execution engine for executing said floating point operation to test said floating point computation unit using said first machine number and said second machine number as said first floating point operand and said second floating point operand.

A design verification system for a floating point computation unit, comprising a processor adapted to execute:

• a generator that receives a definition of a floating point operation to test, said definition comprising a first floating point operand having a first floating point input interval and a second floating point operand, having a second floating point input interval, and a floating point result having a floating point output interval, said input and output intervals having respective upper and lower floating point limits, whereby said first floating point input interval and said second floating point input interval define a region in an operand plane having a first axis and a second axis corresponding respectively to said first floating point operand and said second floating point operand, said generator operative to perform the steps of:
• dividing said region into subrectangles, each of said subrectangles having respective bounds, such that within at least a first subrectangle, a first step size between machine numbers in any first succession along said second axis is constant, and a second step size between said machine numbers in any second succession along said first axis is no less than said first step size;
• defining a reduced interval for said first floating point operand responsively to said upper and lower floating point limits of said second floating point input interval and said floating point output interval;
• selecting a first machine number in said reduced interval;
• defining an integer range responsively to said respective bounds of said first subrectangle, to said first machine number, and to said first step size;
• selecting an integer within said integer range;
• determining a second machine number responsively to said integer and to said first step size;
• and
• an execution engine for executing said floating point operation to test said floating point computation unit using said first machine number and said second machine number as said first floating point operand and said second floating point operand.

A design verification system for an arithmetic floating point unit, comprising a processor adapted to execute:

• a generator for generating a test case, said test case having a first input operand, a second input operand and a floating point arithmetic operation performed thereon to yield an output result;
• wherein said generator is operative to perform the steps of:
• defining a first range that contains a set of first machine numbers;
• defining a second range that contains a set of second machine numbers;
• defining a third range having a lower bound that is a result of a round operation on a minimum value of said output result, and having an upper bound that is a result of said round operation on a maximum value of said output result, wherein instances of said first input operand and said second input operand are in said first range and said second range, respectively;
• defining a subrectangle having a first axis comprising said first range and a second axis comprising said second range;
• subdividing said subrectangle into subregions, each of said subregions having a first property, wherein a first step size along said first axis between successive ones of said first machine numbers is constant, and a second property, wherein a second step size along said second axis between successive ones of said second machine numbers is at least as large as said first step size;
• identifying one of said subregions wherein an integer k exists that satisfies a first inequality (āx−āy)/Δy≦k≦(b′z−ā−ax−āy)/Δy, and wherein a machine number x exists that satisfies second and third inequalities āx≦ x≦ bx, a′z− by≦ x≦b′z−āy;
• choosing an integer n with respect to said one subregion such that
• (a′z− x−āy)/Δy≦n≦(b′z− x−āy)/Δy;
• and
• an execution engine for executing said test case, and wherein said execution engine is operative to execute said arithmetic operation using said machine number x as said first input operand and a quantity (āy+n Δy) as said second input operand;
• wherein
• āx is a smallest one of said first machine numbers,
• āy is a smallest one of said second machine numbers,
• bx is a largest one of said first machine numbers,
• by is a largest one of said second machine numbers,
• a′z is said lower bound of said third range,
• b′z is said upper bound of said third range, and
• Δy is said second step size.