Power semiconductor packaging method and structure

A method of fabricating a power semiconductor chip packaging structure, comprising:

• providing a dielectric film having a first surface and a second surface;
• providing at least one power semiconductor chip with an active surface and an opposing back surface, the chip having one or more contact pads on the active surface;
• applying an adhesion layer adjacent to the first surface of the dielectric film, the adhesion layer comprising a first material;
• adhering the dielectric film to the active surface of the at least one power semiconductor chip by bringing the active surface into physical contact with the adhesion layer;
• forming a patterned electrically conductive layer adjacent to the second surface of the dielectric film, the conductive layer extending through one or more through holes formed in the dielectric film in order to form electrical contact with the one or more contact pads;
• and
• converting the adhesion layer to a second material which can withstand continuous operating temperatures of about 300° C. or greater.