US 2008/0304345 A1 · Semiconductor memory device with reduced number of channels for test operation

Abstract

A semiconductor memory device includes a plurality of memory banks, a data pin for inputting and outputting data, and input/output buffers connected to the data pin. Each of the memory banks has a plurality of memory cells for storing the data. The data pin is enabled and disabled by a pin selection signal. The data pin performs a normal data input/output operation when the pin selection signal is enabled and a termination resistor connected to the data pin is off when the pin selection signal is disabled. The input/output buffers make a termination resistor connected to the data pin off when the pin selection signal is disabled.

Claims14

Dependent claims

A semiconductor memory device comprising:

a plurality of memory banks having a plurality of memory cells for storing data;
and
a data pin which inputs and outputs the data and is enabled or disabled by a pin selection signal.

Dependencies are inferred from the claim text.

Facts

Application

12/005,441Filed 26 Dec 2007

Priority

KR 2007-00559658 Jun 2007

Published

11 Dec 2008

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

G11C 29/48
Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing: arrangements in static stores specially…
G11C 29/1201
Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details: comprising I/O circuitry
G11C 2029/2602
Accessing multiple arrays: concurrent test
G11C 2029/5602
External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor: interface to device under test

Semiconductor memory device with reduced number of channels for test operation

Life of this patent

Semiconductor memory device with reduced number of channels for test operation

Life of this patent

Abstract

Claims14