Synchronous semiconductor memory device having on-die termination circuit and on-die termination method

The device as claimed in 1, wherein the ODT circuit comprises an ODT synchronous buffer adapted to receive an ODT command applied in response to a buffered clock signal generated by buffering the external clock, and outputting a synchronous ODT command in response to a first clock signal delay-locked to the external clock.

The device as claimed in 3, wherein the ODT circuit further comprises:

• an ODT gate adapted to pass through and latch the synchronous ODT command in response to the first clock signal and a second clock signal that has a fixed phase difference with respect to the first clock signal, to generate the ODT up and down signals.

The device as claimed in 3, further comprising a delay-locked loop adapted to generate the first clock signal delay-locked to the external clock.

The device as claimed in 3, wherein the phase difference between the first and second clock signals is based on a half cycle of the external clock.

The device as claimed in 1, wherein the ODT circuit comprises an ODT driver adapted to perform an ODT driving operation synchronized to the external clock, by controlling an ON operation and an OFF operation of a pull-up resistance and a pull-down resistance in response to a state of the ODT up and down signals.

The device as claimed in 9, wherein the plurality of unit drivers comprise:

• at least two pull-up resistances with different values;
• and
• at least two pull-down resistances with different values.

The device as claimed in 1, wherein the ODT circuit comprises an ODT controller adapted to output an up enable signal and a down enable signal in response to an external or internal control signal.

The device as claimed in 11, wherein said ODT controller includes at least one fuse for generating an internal control signal.

The device as claimed in 11, wherein when said ODT controller outputs the up and down enable signals in response to an external control signal, a mode register set code is externally received.