Internal clock driver circuit
AssigneeHynix Semiconductor Inc.
InventorKang Youl Lee
Life of this patent
Estimating the term…
Abstract
An internal clock signal driver circuit includes a delay block that delays a rising clock signal and a falling clock signal, and outputs a delayed rising clock signal and a delayed falling clock signal, a rising DLL clock signal generating block that receives and combines the rising clock signal, the falling clock signal, and the delayed rising clock signal, and outputs a rising DLL clock signal, and a falling DLL clock signal generating block that receives and combines the rising clock signal, the falling clock signal, and the delayed falling clock signal, and outputs a falling DLL clock signal.
Claims23
An internal clock signal driver circuit, comprising:
- a delay block configured to delay a rising clock signal and a falling clock signal, and output a delayed rising clock signal and a delayed falling clock signal;
- a rising DLL clock signal generating block coupled with the delay block, the rising DLL clock signal generating block configured to receive and combine the rising clock signal, the falling clock signal, and the delayed rising clock signal, and output a rising DLL clock signal;
- and
- a falling DLL clock signal generating block coupled with the delay block, the falling DLL clock signal generating block configured to receive and combine the rising clock signal, the falling clock signal, and the delayed falling clock signal, and outputs a falling DLL clock signal.
Dependencies are inferred from the claim text.