Method and apparatus for synchronous clock distribution to a plurality of destinations
AssigneeMicron Technology, Inc.
InventorSeong-hoon Lee
Life of this patent
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Abstract
Circuits, methods and systems are disclosed providing clock synchronization circuits for synchronized clock distribution for a plurality of devices in a semiconductor device. The clock synchronization apparatus includes an independent synchronization circuit and a dependent synchronization circuit. The independent synchronization circuit may provide synchronized clock distribution for a first destination while the dependent synchronization circuit may provide synchronized clock distribution to a second destination. A method for synchronized clock distribution to a plurality of destinations is also described.
Claims30
A circuit, comprising:
- an independent synchronization circuit configured to generate a first destination clock signal substantially synchronized with a source clock signal, wherein the first destination clock signal is provided to a first destination;
- and
- at least one dependent synchronization circuit coupled to the independent synchronization circuit and configured to generate a second destination clock signal substantially synchronized with the source clock signal, wherein the second destination clock signal is provided to a second destination.
A dependent clock synchronization circuit comprising:
- a phase detector module having a first input configured to receive a source clock signal, a second input configured to receive a destination clock signal and an output configured to provide a control signal indicative of the phase difference between the source clock signal and the destination clock signal;
- a control module having an input coupled to the output of the phase detector and an output, the control module configured to provide a clock adjustment signal in the output in accordance with the control signal received in the input;
- and
- a variable delay line module having an input configured to receive a modified clock signal from an independent clock synchronization module, a control terminal configured to receive the clock adjustment signal from the control module output, and an output coupled to a first destination and to the second input of the phase detector module, the variable delay line module configured to adjust the modified clock signal in accordance with the clock adjustment signal to generate the destination clock signal which is sufficiently synchronized wit the source clock signal.
A method comprising:
- modifying a source clock signal, wherein a first destination clock signal is generated;
- synchronizing the first destination clock signal to the source clock signal;
- modifying the first destination clock signal, such that a second destination clock signal is generated;
- and
- synchronizing the second destination clock signal to the source clock signal.
A system comprising a memory device, and a processor coupled to the memory device, at least one of the processor and memory device including a multi-destination clock synchronization circuit, the circuit comprising:
- an independent synchronization circuit configured to generate a first destination clock signal substantially synchronized with a source clock signal, wherein the first destination clock signal is provided to a first destination;
- and
- at least one dependent synchronization circuit coupled to the independent synchronization circuit and configured to generate a second destination clock signal substantially synchronized with the source clock signal, wherein the second destination clock signal is provided to a second destination.
Dependencies are inferred from the claim text.