Delay locked loop circuit

A delay locked loop for providing a delayed clock signal, the delayed clock signal being delayed relative to an input clock signal in response to a variable bias voltage, the delay locked loop comprising:

• first latching circuitry for receiving the input clock signal and a phase shifted clock signal, and for providing a first oscillating signal having a fixed duty cycle at least substantially defined by a first time period between active edges of the input clock signal and the phase shifted clock signal;
• second latching circuitry for receiving the input clock signal and the delayed clock signal, and for providing a second oscillating signal having a variable duty cycle at least substantially defined by a second time period between the active edges of the input clock signal and the delayed clock signal;
• logic circuitry for outputting charge down and charge up control signals that change between active and inactive logic levels based on predefined responsive relationships to logic level changes of the first and second oscillating signals;
• and,
• a charge pump for charging the variable bias voltage in response to the charge up control signal and for discharging the variable bias voltage in response to the charge down control signal.