US 2008/0303567 A1 · DELAY LOCKED LOOP CIRCUIT

Abstract

A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.

Claims13

Dependent claims

1-19. (canceled)

A timing generation circuit, comprising:

a first loop circuit and a second loop circuit, each of which is supplied with a common reference clock signal and each of which outputs a clock signal delayed from the common reference clock signal;
and
a clock generation circuit for generating a delayed clock signal from the clock signals output from the first loop circuit and the second loop circuit, the delayed clock signal including any one of a rising edge and a falling edge with a delay from a rising edge of the common reference clock signal and including the other of the rising edge and the falling edge with a delay from a falling edge of the common reference clock signal.

A timing generation circuit, comprising:

a first loop circuit for receiving a first reference clock signal and outputting a clock signal delayed from the first reference clock signal;
a second loop circuit for receiving a second reference clock signal which is in a phase opposite to that of the first reference clock signal and outputting a clock signal delayed from the second reference clock signal;
and
a clock generation circuit for generating a delayed clock signal from the clock signals output from the first loop circuit and the second loop circuit, the delayed clock signal including any one of a rising edge and a falling edge with a delay from a rising edge of the first reference clock signal and including the other of the rising edge and the falling edge with a delay from a falling edge of the first reference clock signal.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

12/033,707Filed 19 Feb 2008

Priority

JP 2005-0336259 Feb 2005

Published

11 Dec 2008

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

H03L 7/0812
Provided with an additional controlled phase shifter: and where no voltage or current controlled oscillator is used
H03L 7/07
Using a reference signal applied to a frequency- or phase-locked loop: using several loops, e.g. for redundant clock signal generation
H03L 7/0891
The phase or frequency detector generating up-down pulses: the up-down pulses controlling source and sink current generators, e.g. a charge pump
H03L 7/0895
The up-down pulses controlling source and sink current generators, e.g. a charge pump: details of the current generators

Delay locked loop circuit

Life of this patent

Delay locked loop circuit

Life of this patent

Abstract

Claims13