Dll circuit and related method for avoiding stuck state and harmonic locking utilizing a frequency divider and an inverter

A method for locking a second clock signal to a first clock signal, comprising:

• delaying the first clock signal by a delay amount to form the second clock signal;
• dividing a frequency of the first clock signal according to a first frequency dividing factor to form a third clock signal;
• dividing a frequency of the second clock signal according to a second frequency dividing factor to form a fourth clock signal, wherein the first frequency dividing factor is equal to the second frequency dividing factor;
• inverting one of the third clock signal and the fourth clock signal to generate an inverted clock signal while making the other a non-inverted clock signal;
• utilizing a control circuit to compare the inverted clock signal and the non-inverted clock signal to output a control signal for controlling the delay amount, thereby either locking the non-inverted clock signal to the inverted clock signal, or locking the inverted clock signal to the non-inverted clock signal, according to which signal is generated from the second clock signal.

A delay locked loop (DLL) circuit, comprising:

• a delay line for receiving a first clock signal and delaying the first clock signal by a delay amount to generate a second clock signal;
• a control circuit, coupled to the delay line, for controlling the delay line;
• a first frequency divider, coupled to the control circuit, for receiving the first clock signal and dividing a frequency of the first clock signal according to a first frequency dividing factor to form a third clock signal;
• a second frequency divider, coupled to the delay line and the control circuit, for receiving the second clock signal outputted from the delay line and dividing a frequency of the second clock signal according to a second frequency dividing factor to form a fourth clock signal, wherein the first frequency dividing factor is equal to the second frequency dividing factor;
• and
• an inverter, coupling one of the first frequency divider and the second frequency divider to the control circuit, for inverting one of the third clock signal and the fourth clock signal to generate an inverted clock signal while making the other a non-inverted clock signal;
• wherein the control circuit compares the inverted clock signal and the non-inverted clock signal to output a control signal for controlling the delay line, thereby either locking the non-inverted clock signal to the inverted clock signal, or locking the inverted clock signal to the non-inverted clock signal, according to which signal is generated from the second clock signal.