US 2008/0303554 A1 · STRUCTURE FOR A CONFIGURABLE LOW POWER HIGH FAN-IN MULTIPLEXER

Abstract

A configurable, low power high fan-in multiplexer (MUX) and design structure thereof are disclosed. The MUX circuit includes multiple current control elements, which each include multiple inverters coupled to a transmission gate. Each current control element receives a data signal and a select signal that corresponds to the data signal. If a select signal exceeds a threshold value (e.g., a logical “1”), the select signal deactivates a pull-up transistor (e.g., a p-type field effect transistor), and the transmission gate enables the corresponding data signal to provide input to a logic gate (e.g., a NAND gate) coupled to the output of the MUX. If the select signal does not exceed the threshold value, the select signal activates the pull-up transistor, and the transmission gate prevents the corresponding data signal from providing input to the logic gate.

Claims15

Dependent claims

A design structure embodied in a machine readable medium for designing, manufacturing, or testing a multiplexer (MUX) circuit, the design structure comprising:

a logic gate;
a plurality of pull-up transistors coupled in series between a reference voltage and an input of said logic gate;
a plurality of current control elements with outputs coupled to said plurality of pull-up transistors and said input of said logic gate;
a plurality of input signals coupled to respective inputs of said plurality of current control elements, wherein said plurality of input signals comprise a plurality of select signals and a plurality of corresponding data signals;
wherein when a select signal exceeds a threshold value, deactivating a pull-up transistor and enabling a data signal that corresponds to said select signal to provide input to said logic gate;
and
wherein when said select signal does not exceed said threshold value, activating said pull-up transistor and preventing said data signal from providing input to said logic gate.

4 more elements

A hardware description language (HDL) design structure encoded on a machine-readable data storage medium, said HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of an integrated circuit, wherein the HDL design structure comprises:

a first element processed to generate a functional computer-simulated representation of a mechanism for generating a functional computer-simulated representation of a mechanism for receiving a plurality of data signals and a plurality of select signals that correspond to said plurality of data signal, in a computer aided design system for generating a functional design model of a multiplexer (MUX) circuit that includes an output logic gate with inputs coupled to one or more current control elements and one or more corresponding pull up transistors;
a second element processed to generate a functional computer-simulated representation of a mechanism for generating a functional computer-simulated representation of a mechanism for, when a select signal exceeds a threshold value, deactivating a pull-up transistor and enabling a data signal that corresponds to said select signal to provide input to said logic gate;
a third element generating a functional computer-simulated representation of a mechanism for, when said select signal does not exceed said threshold value, activating said pull-up transistor and preventing said data signal from providing input to said logic gate.

Dependencies are inferred from the claim text.

Structure for a configurable low power high fan-in multiplexer

Life of this patent

Structure for a configurable low power high fan-in multiplexer

Life of this patent

Abstract

Claims15