Semiconductor Device and Fabrication Method Thereof

A method for fabricating a complementary semiconductor device comprising:

• forming a gate insulating film on a semiconductor substrate;
• forming a first metal oxide layer having a composition ratio shown with M1xM2yO (where M1=Y, La, Ce, Pr, Nd, Sm, Gd, Th, Dy, Ho, Er, Tm, Yb or Lu, M2=Hf, Zr or Ta, and x/(x+y)>0.12) on the gate insulating film by an ALD method or a CVD method;
• forming a third metal oxide layer having a composition ratio shown with M3zM4wO (where M3=Al, M4=Hf, Zr or Ta, and z/(z+w)>0.14) on the gate insulating film by the ALD method or the CVD method;
• forming a second metal oxide layer and a fourth metal oxide layer on the first metal oxide layer and the third metal oxide layer by the ALD method or the CVD method;
• forming a first conductive layer and a second conductive layer, respectively on the second metal oxide layer and the fourth metal oxide layer;
• forming a gate structure by a lithography process and an etching process;
• and
• forming source/drain regions for n-MISFETs, and source/drain regions for p-MISFETs.

A method for fabricating a complementary semiconductor device comprising:

• forming a gate insulating film on a semiconductor substrate;
• forming a dummy gate on the gate insulating film;
• forming source/drain regions for n-MISFETs, and source/drain regions for p-MISFETs;
• removing the dummy gate;
• forming a first metal oxide layer having a composition ratio shown with M1xM2yO (where M1=Y, La, Ce, Pr, Nd, Sm, Gd, Th, Dy, Ho, Er, Tm, Yb or Lu, M2=Hf, Zr or Ta, and x/(x+y)>0.12)on the gate insulating film by an ALD method or a CVD method;
• forming a third metal oxide layer having a composition ratio shown with M3zM4wO (where M3=Al, M4=Hf, Zr or Ta, and z/(z+w)>0.14) on the gate insulating film by the ALD method or the CVD method;
• forming a second metal oxide layer and a fourth metal oxide layer on the first metal oxide layer and the third metal oxide layer by the ALD method or the CVD method;
• forming a first conductive layer and a second conductive layer, respectively on the second metal oxide layer and the fourth metal oxide layer;
• and
• forming a gate structure by a lithography process and an etching process.