US 2008/0303087 A1Published application

Semiconductor device with integrated trench lateral power MOSFETs and planar devices

AssigneeFuji Electric Co., Ltd.

InventorsAkio Sugi, Naoto Fujishima, Mutsumi Kitamura, Katsuya Tabuchi, Setsuko Wakimoto

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Abstract

Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.

Claims23

Dependent claims

A manufacturing method of a semiconductor device comprising at least one trench lateral power MOSFET on a semiconductor substrate, comprising a first gate oxide film and first gate electrodes that are positioned in a trench, a first drain region positioned under a bottom surface of the trench, first source regions positioned on both sides of the trench, an extended drain region positioned between the first drain region and the first source regions, a first drain electrode connected electrically to the first drain region, and first source electrodes connected electrically to the respective first source regions, and at least one planar MOSFET positioned on the semiconductor substrate, comprising a second gate oxide film and a second gate electrode that are positioned on a surface of the semiconductor substrate, a second drain region and a second source region that are positioned in a surface layer of the semiconductor substrate on both sides of the second gate electrode, a second drain electrode connected electrically to the second drain region, and a second source electrode connected electrically to the second source region, the manufacturing method comprising:

forming the trench in the semiconductor substrate;
forming the extended drain region;
forming the first gate oxide film and the second gate oxide film;
forming first gate electrodes and the second gate electrode;
forming the first drain region, first source regions, the second drain region, and the second source region;
laying an interlayer insulating film over the surface of the semiconductor substrate;
etching the interlayer insulating film to expose the first drain region under the bottom surface of the trench;
filling the inside of the trench with a polysilicon layer that is in contact with the first drain region;
laying a passivation film over the surface of the semiconductor substrate;
etching the passivation film and the interlayer insulating film to expose the polysilicon layer, the first source regions, the second drain region, and the second source region;
and
laying a metal layer on the passivation film and patterning the metal layer to form the first drain electrode, first source electrodes, the second drain electrode, and the second source electrode that are in contact with the polysilicon layer, the first source regions, the second drain region, and the second source region, respectively.

9 more elements

A semiconductor device comprising:

a trench lateral power MOSFET on a semiconductor substrate, comprising
a first gate oxide film and first gate electrodes that are positioned in a trench;
a first source region of a second conductivity type positioned under a bottom surface of the trench;
first drain regions of a second conductivity type positioned on both sides of the trench;
an extended drain region of a second conductivity type and a base region of a first conductivity type to serve as channel regions, the extended drain region and the base region being positioned between the first source region and the first drain regions;
first drain electrodes connected electrically to the respective first drain regions;
and
a first source electrode connected electrically to the first source region;
a first planar MOSFET positioned on the semiconductor substrate, comprising
a second gate oxide film and a second gate electrode that are positioned on a surface of the semiconductor substrate;
a second drain region of a first conductivity type and a second source region of a first conductivity type that are positioned in a surface layer of the semiconductor substrate on both sides of the second gate electrode;
a second drain electrode connected electrically to the second drain region;
and
a second source electrode connected electrically to the second source region;
and
a second planar MOSFET positioned on the semiconductor substrate, comprising a third gate oxide film and a third gate electrode that are positioned on the surface of the semiconductor substrate;
a third drain region of a second conductivity type and a third source region of a second conductivity type that are positioned in the surface layer of the semiconductor substrate on both sides of the third gate electrode;
a third drain electrode connected electrically to the third drain region;
and a third source electrode connected electrically to the third source region,
wherein the first drain electrodes, the first source electrode, the second drain electrode, the second source electrode, the third drain electrode, and the third source electrode are formed by patterning the same metal layer.

17 more elements

A semiconductor device comprising:

a first trench lateral power MOSFET on a semiconductor substrate, comprising
a first gate oxide film and first gate electrodes that are positioned in a first trench;
a first source region of a second conductivity type positioned under a bottom surface of the first trench;
first drain regions of a second conductivity type positioned on both sides of the first trench;
a first extended drain region of a second conductivity type and a first base region of a first conductivity type to serve as channel regions, the first extended drain region and the first base region being positioned between the first source region and the first drain regions;
first drain electrodes connected electrically to the respective first drain regions;
and
a first source electrode connected electrically to the first source region;
a second trench lateral power MOSFET positioned on the semiconductor substrate, comprising
a second gate oxide film and second gate electrodes that are positioned in a second trench;
a second source region of a first conductivity type positioned under a bottom surface of the second trench;
second drain regions of a first conductivity type positioned on both sides of the second trench;
a second extended drain region of a first conductivity type and a second base region of a second conductivity type to serve as channel regions, the second extended drain region and the second base region being positioned between the second source region and the second drain regions;
second drain electrodes connected electrically to the respective second drain regions;
and
a second source electrode connected electrically to the second source region;
and
a planar MOSFET positioned on the semiconductor substrate, comprising
a third gate oxide film and a third gate electrode that are positioned on a surface of the semiconductor substrate;
a third drain region of a second conductivity type and a third source region of a second conductivity type that are positioned in a surface layer of the semiconductor substrate on both sides of the third gate electrode;
a third drain electrode connected electrically to the third drain region;
and
a third source electrode connected electrically to the third source region,
wherein the first drain electrodes, the first source electrode, the second drain electrodes, the second source electrode, the third drain electrode, and the third source electrode are formed by patterning a same metal layer.

21 more elements

A semiconductor device comprising:

a first trench lateral power MOSFET on a semiconductor substrate, comprising
a first gate oxide film and first gate electrodes that are positioned in a first trench;
a first source region of a second conductivity type positioned under a bottom surface of the first trench;
first drain regions of a second conductivity type positioned on both sides of the first trench;
a first extended drain region of a second conductivity type and a first base region of a first conductivity type to serve as channel regions, the first extended drain region and the first base region being positioned between the first source region and the first drain regions;
first drain electrodes connected electrically to the respective first drain regions;
and
a first source electrode connected electrically to the first source region;
a second trench lateral power MOSFET positioned on the semiconductor substrate, comprising
a second gate oxide film and second gate electrodes that are positioned in a second trench;
a second source region of a first conductivity type positioned under a bottom surface of the second trench;
second drain regions of a first conductivity type positioned on both sides of the second trench;
a second extended drain region of a first conductivity type and a second base region of a second conductivity type to serve as channel regions, the second extended drain region and the second base region being positioned between the second source region and the second drain regions;
second drain electrodes connected electrically to the respective second drain regions;
and
a second source electrode connected electrically to the second source region;
a first planar MOSFET positioned on the semiconductor substrate, comprising
a third gate oxide film and a third gate electrode that are positioned on a surface of the semiconductor substrate;
a third drain region of a second conductivity type and a third source region of a second conductivity type that are positioned in a surface layer of the semiconductor substrate on both sides of the third gate electrode;
a third drain electrode connected electrically to the third drain region;
and
a third source electrode connected electrically to the third source region;
and
a second planar MOSFET positioned on the semiconductor substrate, comprising
a fourth gate oxide film and a fourth gate electrode that are positioned on the surface of the semiconductor substrate;
a fourth drain region of a first conductivity type and a fourth source region of a first conductivity type that are positioned in the surface layer of the semiconductor substrate on both sides of the fourth gate electrode;
a fourth drain electrode connected electrically to the fourth drain region;
a fourth source electrode connected electrically to the fourth source region,
wherein the first drain electrodes, the first source electrode, the second drain electrodes, the second source electrode, the third drain electrode, the third source electrode, the fourth drain electrode, and the fourth source electrode are formed by patterning a same metal layer, and
wherein the first gate electrodes, the second gate electrodes, the third gate electrode, and the fourth gate electrode are formed by patterning a polysilicon layer formed on the surface of the semiconductor substrate and inside the trench.

27 more elements

A semiconductor device comprising:

a first trench lateral power MOSFET on a semiconductor substrate, comprising
a first gate oxide film and first gate electrodes that are positioned in a first trench;
a first source region of a second conductivity type positioned under a bottom surface of the first trench;
first drain regions of a second conductivity type positioned on both sides of the first trench;
a first extended drain region of a second conductivity type and a first base region of a first conductivity type to serve as channel regions, the first extended drain region and the first base region being positioned between the first source region and the first drain regions;
first drain electrodes connected electrically to the respective first drain regions;
and
a first source electrode connected electrically to the first source region;
a second trench lateral power MOSFET positioned on the semiconductor substrate, comprising
a second gate oxide film and second gate electrodes that are positioned in a second trench;
a second source region of a first conductivity type positioned under a bottom surface of the second trench;
second drain regions of a first conductivity type positioned on both sides of the second trench;
a second extended drain region of a first conductivity type and a second base region of a second conductivity type to serve as channel regions, the second extended drain region and the second base region being positioned between the second source region and the second drain regions;
second drain electrodes connected electrically to the respective second drain regions;
and
a second source electrode connected electrically to the second source region;
a first planar MOSFET positioned on the semiconductor substrate, comprising
a third gate oxide film and a third gate electrode that are positioned on a surface of the semiconductor substrate;
a third drain region of a second conductivity type and a third source region of a second conductivity type that are positioned in a surface layer of the semiconductor substrate on both sides of the third gate electrode;
a third drain electrode connected electrically to the third drain region;
and
a third source electrode connected electrically to the third source region;
and
a second planar MOSFET positioned on the semiconductor substrate, comprising
a fourth gate oxide film and a fourth gate electrode that are positioned on the surface of the semiconductor substrate;
a fourth drain region of a first conductivity type and a fourth source region of a first conductivity type that are positioned in the surface layer of the semiconductor substrate on both sides of the fourth gate electrode;
a fourth drain electrode connected electrically to the fourth drain region;
a fourth source electrode connected electrically to the fourth source region;
and
a first body region that is positioned under the bottom surface of the first trench and has a same conductivity type as the first base region,
wherein the first drain electrodes, the first source electrode, the second drain electrodes, the second source electrode, the third drain electrode, the third source electrode, the fourth drain electrode, and the fourth source electrode are formed by patterning a same metal layer.

28 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/149,016Filed 24 Apr 2008
Priority: JP 2002-801516 Jan 2002
Published: 11 Dec 2008
Term ends: Not estimatedThe source records don’t support an estimate.

Classification20 codes

H10D 30/658
Lateral dmos [ldmos] fets: having trench gate electrodes
H10D 30/0221
Of FETs having insulated gates [IGFET]: having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or…
H10D 30/603
Having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs: having asymmetry in the channel direction, e.g. lateral…
H10D 30/608
Having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs: having non-planar bodies, e.g. having recessed gate electrodes

Family

Application10/334,127Division · filed 31 Dec 2002
Application11/010,508Division · filed 14 Dec 2004
Application12/149,016Division
US 2003/0164527 A1Published application
US 2005/0087800 A1Published application
US 6,858,500 B2Related patent
US 7,365,392 B2Related patent
US 2008/0303087 A1This patent

From the US filing history. Foreign family members aren’t listed.

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