Split gate memory cell using sidewall spacers

A method of forming a split gate memory device, comprising:

• providing a semiconductor layer;
• providing a bitcell stack overlying the semiconductor layer, wherein the bitcell stack includes at least a first layer, a second layer, and a third layer, wherein the second layer comprises a charge storage material of nanocrystals and high temperature oxide;
• providing a sidewall spacer height determining layer overlying the bitcell stack;
• defining a bitcell length within the bitcell stack and the sidewall spacer height determining layer, wherein defining also includes exposing the semiconductor layer on opposing sides of the bitcell stack defined by the bitcell length, the bitcell length including a first gate length, a second gate length, and a gap length of a split gate bitcell;
• forming a sacrificial layer over the bitcell stack and the exposed portions of the semiconductor layer, the sacrificial layer being selectively etchable with respect to the bitcell stack;
• planarizing the sacrificial layer to expose a surface of the sidewall spacer height determining layer overlying the bitcell stack;
• removing the sidewall spacer height determining layer overlying the bitcell stack, wherein removing the sidewall spacer height determining layer exposes sidewall portions of the sacrificial layer;
• forming sidewall spacers along the exposed sidewall portions of the sacrificial layer, wherein bottom portions of the sidewall spacers proximate the third layer of the bitcell stack are separated from one another by at least the gap length;
• etching the third layer of the bitcell stack selective to the sidewall spacers, wherein the etching forms a gap within the third layer that splits the third layer into a first gate and a second gate which together form a split gate bitcell stack;
• etching through the second layer of the bitcell stack, wherein the etching extends the gap and separates the second layer into first and second separate regions of the split gate bitcell stack, the extended gap being devoid of charge storage material, and wherein one of the first and second separate regions of the second layer functions as a storage region of the split gate bitcell stack;
• depositing a dielectric material over the gap and performing an etch back of the dielectric material to expose a top surface of the sacrificial layer;
• and
• removing the sacrificial layer to expose sidewalls of the split gate bitcell stack.

A split gate memory device formed by the method comprising:

• providing a semiconductor layer;
• providing a bitcell stack overlying the semiconductor layer, wherein the bitcell stack includes at least a first layer, a second layer, and a third layer, wherein the second layer comprises a charge storage material;
• providing a sidewall spacer height determining layer overlying the bitcell stack;
• defining a bitcell length within the bitcell stack and the sidewall spacer height determining layer, wherein defining also includes exposing the semiconductor layer on opposing sides of the bitcell stack defined by the bitcell length, the bitcell length including a first gate length, a second gate length, and a gap length of a split gate bitcell;
• forming a sacrificial layer over the bitcell stack and the exposed portions of the semiconductor layer, the sacrificial layer being selectively etchable with respect to the bitcell stack;
• planarizing the sacrificial layer to expose a surface of the sidewall spacer height determining layer overlying the bitcell stack;
• removing the sidewall spacer height determining layer overlying the bitcell stack, wherein removing the sidewall spacer height determining layer exposes sidewall portions of the sacrificial layer;
• forming sidewall spacers along the exposed sidewall portions of the sacrificial layer, wherein bottom portions of the sidewall spacers proximate the third layer of the bitcell stack are separated from one another by at least the gap length;
• etching the third layer of the bitcell stack selective to the sidewall spacers, wherein the etching forms a gap within the third layer that splits the third layer into a first gate and a second gate which together form a split gate bitcell stack;
• etching through the second layer of the bitcell stack, wherein the etching extends the gap and separates the second layer into first and second separate regions of the split gate bitcell stack, the extended gap being devoid of charge storage material;
• depositing a dielectric material over the gap and performing an etch back of the dielectric material to expose a top surface of the sacrificial layer;
• and
• removing the sacrificial layer to expose sidewalls of the split gate bitcell stack.