Method for generation, placement, and routing of test structures in test chips

A method of generating and placing of test structures in test chips comprising:

• establishing, for one or more device types of a given semiconductor technology, a predefined set of keywords in which each keyword defines (a) one or more pad allocations for each test structure of a given device type, (b) a number quantity of test structures for the given device type, (c) placement information of the test structures relative to one or more pad allocations of at least one pad array, (d) test structure terminal routing requirements relative to allocated pads of the one or more pad allocations of the at least one pad array, and (e) identification of a type of test that is to be performed with a corresponding test structure, wherein the type of test includes at least one corresponding generation, placement, and terminal routing requirement;
• creating a control data set for the one or more device types, wherein the control data set includes (i) a set of keywords and (ii) parameter geometries for corresponding ones of test structures associated with the set of keywords;
• generating a test structure layout in response to the control data set;
• and
• placing the test structure layout within a given pad array layout of the at least one pad array as a function of the set of keywords and implementing a corresponding test structure terminal routing, wherein the pad array layout is configured for enabling a fabrication of corresponding test structures in test chips.

A computer program product comprising instructions stored on a computer readable media and executable by a computer, the instructions for carrying out a method of generating and placing of test structures in test chips comprising:

• creating a control data set for one or more device types, wherein the control data set includes (i) a set of keywords and (ii) parameter geometries for corresponding ones of test structures associated with the set of keywords, and wherein the keywords each define (a) one or more pad allocations for each test structure of a given device type, (b) a number quantity of test structures for the given device type, and (c) placement information of the test structures relative to one or more pad allocations of at least one pad array;
• generating a test structure layout in response to the control data set;
• and
• placing the test structure layout within a given pad array layout of the at least one pad array as a function of the set of keywords, wherein the pad array layout is configured for enabling a fabrication of corresponding test structures in test chips.