Design Structure for Switching Digital Circuit Clock Net Driver Without Losing Clock Pulses

A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit with glitchless clock selection logic, the design structure comprising:

• a plurality of clock signals, each of the plurality of clock signals having a different clock frequency;
• a clock selection signal that indicates a change in clock selection from a first clock signal to a second clock signal, the first clock signal and the second clock signal included in the plurality of clock signals;
• detection logic that, after the receiving of the clock selection signal, detects that the first clock signal's clock edge aligns with the second clock signal's clock edge;
• and
• selection logic that selects the second clock signal in response to the detection of the first clock signal's clock edge aligning with the second clock signal's clock edge.

A hardware description language (HDL) design structure encoded on a machine-readable data storage medium, said HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a (device name), wherein said HDL design structure comprises:

• a first element processed to generate a functional computer-simulated representation of a plurality of clock signals, each of the plurality of clock signals having a different clock frequency;
• a second element processed to generate a functional computer-simulated representation of a clock selection signal from one of the processors that indicates a change in clock selection from a first clock signal to a second clock signal, the first clock signal and the second clock signal included in the plurality of clock signals;
• a third element processed to generate a functional computer-simulated representation of detecting, after receiving the clock selection signal, that the first clock signal's clock edge aligns with the second clock signal's clock edge;
• and
• a fourth element processed to generate a functional computer-simulated representation of selecting the second clock signal in response to the detection of the first clock signal's clock edge aligning with the second clock signal's clock edge.