Data processing system, cache system and method for updating an invalid coherency state in response to snooping an operation

A cache memory for a cache coherent data processing system including at least first and second coherency domains each including at least one processing unit, wherein said first coherency domain includes the cache memory and said second coherency domain includes another coherent cache memory, said cache memory comprising:

• a cache controller;
• a data array including a data storage location for caching a memory block;
• and
• a cache directory including:
• a tag field for storing an address tag in association with said memory block;
• a coherency state field associated with said tag field and said data storage location, wherein said coherency state field has a plurality of possible coherency states including a first and second data-invalid coherency states, wherein said first data-invalid coherency state indicates that said address tag is valid and that said storage location does not contain valid data and a second data-invalid coherency state indicates that said address tag is valid, that said storage location does not contain valid data, and whether a target memory block associated with said address tag is likely cached within said first coherency domain;
• wherein said cache controller updates said coherency state field from said first data-invalid coherency state to said second data-invalid coherency state in response to snooping in response to snooping an exclusive access operation specifying a target address matching said address tag and containing an indication of a relative domain location of a requester that initiated said exclusive access operation.

A cache coherent data processing system, comprising:

• an interconnect fabric;
• first and second coherency domains coupled by said interconnect fabric, wherein said first coherency domain includes at least a first processing unit supported by a first cache memory and said second coherency domain includes a second processing unit supported by a coherent second cache memory, wherein said first cache memory within said first coherency domain of said data processing system includes:
• a cache directory including:
• a tag field for storing an address tag in association with said memory block;
• a coherency state field associated with said tag field and said data storage location, wherein said coherency state field has a plurality of possible coherency states including a first and second data-invalid coherency states, wherein said first data-invalid coherency state indicates that said address tag is valid and that said storage location does not contain valid data and a second data-invalid coherency state indicates that said address tag is valid, that said storage location does not contain valid data, and whether a target memory block associated with said address tag is likely cached within said first coherency domain;
• wherein said cache controller updates said coherency state field from said first data-invalid coherency state to said second data-invalid coherency state in response to snooping in response to snooping an exclusive access operation specifying a target address matching said address tag and containing an indication of a relative domain location of a requester that initiated said exclusive access operation.