Data Transfer Apparatus and Data Transfer Method

A data transfer method that transfers data to a memory connected to a processor from a data transfer unit that is connected to the memory via a plurality of buses, comprising:

• the data transfer unit performing data transfer processing that transfers data to be transferred from a device having the data to be transferred to a first storage area of the memory by bypassing the processor;
• upon completion of the data transfer processing, the data transfer unit writing status data indicating completion of the data transfer processing in a second storage area of the memory;
• the data transfer unit outputting a predetermined interrupt signal to the processor after writing the status data;
• and
• referring to the second storage area in response to the predetermined interrupt signal to the processor, performing determination processing that determines whether or not the status data is written, repeatedly referring to the second storage area when a result of the determination processing is that the status data is not written, and reading out the data to be transferred in the first storage area and erasing the status data in the second storage area when the status data is written.

A computer having PC architecture, comprising

• a processor;
• a main memory connected to the processor;
• a direct memory access controller that is connected to the main memory through a plurality of buses and is configured to perform data transfer processing to transfer data to be transferred from a device having the data to be transferred to a transfer data storage area of the main memory by direct memory access that bypasses the processor, and when the data transfer processing finishes, write status data indicating completion of the data transfer processing in a completion status storage area of the main memory, and output a predetermined interrupt signal to the processor after writing the status data;
• and
• an interrupt handler configured to refer to the completion status storage area in response to the predetermined interrupt signal sent to the processor and perform processing that determines whether or not the status data is written, repeat the reference to the completion status storage area when the determination processing result indicates that the status data is not written, and read out the data to be transferred in the transfer data storage area and erase the status data in the completion status storage area when the status data is written.