Single-poly non-volatile memory device and its operation method

A method for erasing a single-poly, P-channel non-volatile memory unit, wherein the single-poly, P-channel non-volatile memory unit comprises an N well, a P+ source doping region, a P+ drain doping region in the N well, a P channel between the P+ source doping region and P+ drain doping region, the P channel comprising a first channel region and a second channel region that is contiguous to the first channel region and is of the same conductivity type as said first channel region;

• a gate dielectric layer disposed only on the first channel region;
• a control gate stacked on the gate dielectric layer;
• and a dielectric spacer comprising a floating charge trapping medium disposed on sidewalls of the control gate, wherein said charge trapping medium is situated directly above said second channel region;
• the method comprising:
• grounding the source doping region VS
• connecting the drain doping region to a drain voltage VD being negative with respect to the source voltage VS;
• connecting the N well to a N well voltage VNW being positive with respect to the source voltage VS;
• and
• connecting the control gate to a gate voltage VG being negative with respect to the source voltage VS such that electrons trapped in the charge trapping medium are erased by means of CHannel Induced Secondary Hole Injection (CHISHI).