Lithography evaluating method, semiconductor device manufacturing method and program medium
AssigneeKabushi Kaisha Toshiba
InventorsKazuo TAWARAYAMA, Shunko Magoshi
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Abstract
A lithography evaluating method comprises preparing a substrate, the substrate including a semiconductor substrate and a wiring structure including at least one wiring layer formed on the semiconductor substrate, partitioning the substrate into a plurality of regions to be evaluated, and obtaining a value of property relating to the wiring structure previously, and evaluating proximity effect on each of the plurality of regions to be evaluated based on the value of the property relating to the wiring structure.
Claims20
A lithography evaluating method comprising:
- preparing a substrate, the substrate including a semiconductor substrate and a wiring structure including at least one wiring layer formed on the semiconductor substrate;
- partitioning the substrate into a plurality of regions to be evaluated;
- and
- obtaining a value of property relating to the wiring structure previously, and evaluating proximity effect on each of the plurality of regions to be evaluated based on the value of the property relating to the wiring structure.
A lithography evaluating method comprising:
- preparing a substrate, the substrate including a semiconductor substrate and a wiring structure including at least one wiring layer formed on the semiconductor substrate;
- and
- obtaining a relationship between property relating to the number and thickness of the at least one wiring layer and property relating to reflection energy on a surface of the substrate of charged particles reflected on the wiring structure when a resist formed on the substrate is irradiated with a charged particle beam previously, and obtaining a relationship between size error of a resist pattern to be formed on the substrate by lithography process using a charged particle beam and value of the property relating to the number and thickness of the at least one wiring layer based on the property relating to the number and thickness of the at least one wiring layer and the property relating to the reflection energy on the surface of the substrate of charged particles.
A lithography evaluating method comprising:
- preparing a substrate, the substrate including a semiconductor substrate and a wiring structure including at least one wiring layer formed on the semiconductor substrate;
- partitioning the substrate into a plurality of regions to be evaluated;
- and
- evaluating proximity effect on each of the plurality of regions to be evaluated based on a relationship between size error of a resist pattern to be formed on the substrate by lithography process using a charged particle beam and a value of property relating to the number and thickness of the at least one wiring layer.
(canceled)
(canceled)
A computer program product configured to store program instructions for execution on the computer system enabling the computer system to perform the operations of:
- reading in data relating to a substrate, the substrate including a semiconductor substrate and a wiring structure including at least one wiring layer formed on the semiconductor substrate;
- partitioning the substrate into a plurality of regions to be evaluated;
- and
- obtaining a value of property relating to the number and thickness of the at least one wiring layer included in the wiring structure previously and evaluating proximity effect on each of the plurality of regions to be evaluated.
(canceled)
Dependencies are inferred from the claim text.