Self-Clearing Asynchronous Interrupt Edge Detect Latching Register

A digital system having at least a first clock domain and second clock domain, comprising:

• a clock generator for generating a first clock signal and another clock generator for generating a second clock signal, wherein the second clock signal is generated asynchronously with the first clock signal;
• target circuitry in the second clock domain connected to operate synchronously to the second clock signal;
• control circuitry in the first clock domain responsive to the first clock signal for generating a target control signal for controlling the target circuitry;
• toggle circuitry connected to receive the target control signal being operable to form a tattle-tail signal such that the tattle-tail signal is toggled in response to each assertion of the target control signal;
• and
• edge detection circuitry connected to receive the tattle-tail signal and the second clock signal to form a synchronized target control signal such that a pulse is formed synchronously to the second clock signal in response to each transition of the tattle-tail signal, the synchronized target control signal connected to control the target circuitry.

A digital system comprising:

• a clock generator in a processor clock domain for generating a processor clock signal and a clock generator in a target clock domain for generating a target clock signal, wherein the target clock signal is generated asynchronously with the processor clock signal;
• a clear-on-read (COR) register connected to operate synchronously to the target clock signal;
• a processor responsive to the processor clock signal for generating a read control signal for reading the COR register;
• tattle-tail circuitry connected to receive the read control signal being operable to form a tattle-tail signal such that the tattle-tail signal is toggled in response to each assertion of the read control signal;
• edge detection circuitry connected to receive the tattle-tail signal and the target clock signal to form a synchronized target control signal such that a pulse is formed synchronously to the target clock signal in response to each transition of the tattle-tail signal;
• a feedback register connected to receive and latch the contents of the COR register responsive to the processor clock signal and connected to provide the latched contents to the processor to satisfy a read request;
• and
• clear-on-read logic connected to receive for each bit of the COR register a corresponding bit of the feedback register and connected to receive the synchronized target control signal and operable to form a reset signal for each bit of the COR register that has a first logic value only if the corresponding bit of the feedback latch has the first logic value when the target control signal is asserted and when the COR register is being accessed by the processor.

A digital system having at least a first clock domain and a second clock domain, comprising:

• a clock generator for generating a first clock signal for use in the first clock domain and a clock generator for generating a second clock signal for use the second clock domain, wherein the second clock is generated asynchronously with the first clock signal;
• means for generating a first domain control signal pulse in response to the first clock signal for controlling the target;
• means for detecting each time the first domain control signal pulse is asserted;
• means for forming a second domain control signal pulse synchronized to the second clock signal in response to each detected assertion of the first domain control signal pulse;
• and
• means for controlling the target in the second clock domain using the second domain control signal pulse.