Frequency Monitor
AssigneeAtmel Corporation
InventorJean-Francois GUIRAMAND
Life of this patent
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Abstract
A method and system for monitoring a frequency of a clock signal is disclosed. The method and system comprise dividing a clock signal into a plurality of clock signal components. The method and system further comprise adding a delay to each of the clock signal components and comparing the plurality of signal components with each of the delayed clock signal components to monitor whether the clock signal is within a predetermined frequency range. The method and system includes providing an output signal indicative of a condition of the clock signal based upon the comparing step.
Claims17
A method comprising:
- dividing a clock signal into a plurality of clock signal components;
- adding a delay to each of the clock signal components;
- comparing the plurality of signal components with each of the delayed clock signal components to monitor whether clock signal within a predetermined frequency range;
- and providing an output signal indicative of a condition of the clock signal based upon the comparing step.
A frequency monitor comprising:
- a controller for receiving the clock signal and dividing the signal into a plurality of clock pulses;
- a plurality of delays for receiving the plurality of clock pulses, and providing a plurality of delayed clock pulses;
- a plurality of monitors for receiving the plurality of delayed clock pulses, for receiving the plurality of clock pulses and for providing output signals indicative of a condition of the clock signal;
- and
- a combiner for receiving the output signals from the plurality of monitors and providing an error flag indicative of the condition of the clock signal.
A frequency monitor circuit comprising:
- a control circuit for dividing an input clock signal into a plurality of clock signal components;
- a bias cell for providing a reference voltage;
- a delay cell system controlled by the bias cell, for receiving the divided clock signal and providing a plurality of divided delayed input clock signal components;
- and
- a signal processing system for receiving divided input clock signal components and the delayed divided input clock signal components to provide an indication of a condition of the input clock signal.
A frequency monitor comprising:
- a controller for receiving the clock signal and dividing the signal into odd and even clock pulses;
- first and second delays for receiving the odd and even pulses, and providing a plurality of delayed odd and even clock pulses;
- first and second monitors for receiving the plurality of delayed odd and even clock pulses, for receiving the plurality of odd and even pulses and for providing output signals indicative of a condition of the clock signal;
- and
- a combiner for receiving the output signals and providing an error flag indicative of the condition of the clock signal.
An integrated circuit comprising:
- a functional unit;
- and
- a frequency monitor coupled to the functional unit, the frequency monitor comprising a controller for receiving the clock signal and dividing the signal into a plurality of clock pulses;
- a plurality of delays for receiving the plurality of clock pulses, and providing a plurality of delayed clock pulses;
- a plurality of monitors for receiving the plurality of delayed clock pulses, for receiving the plurality of clock pulses and for providing output signals indicative of a condition of the clock signal;
- and a combiner for receiving the output signals from the plurality of monitors and providing an error flag indicative of the condition of the clock signal.
Dependencies are inferred from the claim text.