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US 2008/0290519 A1Published application
Dual liner capping layer interconnect structure
AssigneeInternational Business Machines Corporation
InventorsChih-Chao Yang, Haining Yang, Keith Kwong Hon Wong
Life of this patent
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Abstract
A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms in thickness. Each dielectric layer is plasma treated prior to depositing each succeeding dielectric layer such that the dielectric cap has an internal tensile stress.
Claims8
A semiconductor device comprising;
- a dielectric layer with at least one conductive interconnect partially embedded therein;
- and
- a tensile capping layer in contact with said at least one conductive interconnect.
8-25. (canceled)
Dependencies are inferred from the claim text.