Chip Scale Package and Method of Assembling the Same
AssigneeUnited Test and Assembly Center Ltd.
InventorsHien Boon Tan, Chuen Khiang Wang, Rahamat Bidin, Anthony Yi Sheng Sun, Desmond Yok Rue Chong, Ravi Kanth Kolan
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Abstract
A method of producing a chip scale package is disclosed. The method includes dicing a wafer into a plurality of chip arrays, each array including two or more integrated circuit chips. The method further includes mounting each array on a substrate and dicing each array, attached to the substrate, into individual chip scale packages, each individual chip scale package including only one integrated circuit chip.
Claims12
A method of producing chip scale package, comprising:
- attaching an array of two or more integrated circuit chips on a substrate;
- dicing the array, attached to the substrate, into individual chip scale packages, each chip scale package comprising only one integrated circuit chip.
A method of producing a chip scale package, comprising:
- providing a wafer, the wafer comprising a plurality of integrated circuit chips;
- dicing the wafer into a plurality of chip arrays, each array comprising two or more integrated circuit chips;
- attaching each chip array on a substrate;
- dicing each array, attached to the substrate, into individual chip scale packages, each individual chip scale package comprising only one integrated circuit chip.
A method of producing a chip scale package, comprising:
- providing a wafer, the wafer comprising a plurality of integrated circuit chips, each integrated circuit chip comprising
- a plurality of bond pads aligned on an upper surface of the integrated circuit chip and
- a plurality of conductive bumps formed on the plurality of bond pads;
- dicing the wafer into a plurality of chip arrays, each array comprising two or more integrated circuit chips;
- mounting each array on a substrate such that the bumps align with corresponding solder pad openings on an upper surface of the substrate;
- reflowing the integrated circuit chips of each array, thereby melting the bumps and establishing a conductive joint between the integrated circuit chips and the substrate;
- under fill encapsulating the integrated circuit chips and the substrate;
- and
- dicing the array, joined to the substrate, into individual chip scale packages, each comprising only one integrated circuit chip.
A multi-chip array package, comprising:
- a substrate;
- and
- a chip array, comprising two or more integrated circuit chips, flip-chip mounted on the substrate.
Dependencies are inferred from the claim text.