Chip embedded printed circuit board and fabricating method thereof
AssigneeKorea Electronics Technology Institute
InventorsSe Hoon Park, Jun Chul Kim, Jong Chul Park, Nam Kee Kang, Woo Sung Lee, Chan Sei Yoo
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AssigneeKorea Electronics Technology Institute
InventorsSe Hoon Park, Jun Chul Kim, Jong Chul Park, Nam Kee Kang, Woo Sung Lee, Chan Sei Yoo
Estimating the term…
The chip embedded printed circuit board and a fabricating method thereof are disclosed, wherein a circuit pattern is formed by depositing a metal layer on a support layer, a semiconductor chip is packaged on a support layer to wrap the semiconductor chip and the circuit pattern on the support layer and to form an isolation layer, a via hole filled with conductive material is formed through the isolation layer for interlayer electrical connection, part of the support layer is selectively removed to form a plated heat sink, such that a packaging process can be performed in a very planar state and the plated heat sink can be integrated with a printed circuit board.
A fabricating method for chip embedded printed circuit board comprising:
A fabricating method for chip embedded printed circuit board comprising:
A chip embedded printed circuit board (PCB) wherein a circuit pattern is formed on a plated heat sink, a semiconductor chip is packaged on the circuit pattern, an isolation layer is formed on the plated heat sink wrapping the circuit pattern and the semiconductor chip, a metal layer is formed on the isolation layer, a via hole is formed on the circuit pattern through the isolation layer and the metal layer, and a plating layer is formed at an inner wall of the via hole.
A chip embedded printed circuit board wherein a first circuit pattern is formed on a plated heat sink, a first isolation layer is formed on the plated heat sink wrapping the first isolation layer, a second circuit pattern is formed on the first isolation layer, a via hole is formed on the first circuit pattern through the first isolation layer and the second circuit pattern, a first plating layer if formed at an inner wall of the first via hole, a semiconductor chip is packaged on the first isolation layer, a second isolation layer is formed on the first isolation layer wrapping the second circuit pattern and the semiconductor chip;
Dependencies are inferred from the claim text.