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US 2008/0290386 A1Published application
Floating gate memory device with increased coupling coefficient
AssigneeCypress Semiconductor Corporation
InventorFredrick Jenne
Life of this patent
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Abstract
Methods and apparatus for increasing the coupling coefficient of a floating gate memory device includes an MOS capacitors with self-aligning gate structures that provide increased capacitance per unit area over conventional MOS capacitors.
Claims20
A device, comprising:
- a self-aligning gate structure disposed upon a semiconductor substrate, the self-aligning gate structure comprising a plurality of gate fingers, wherein each gate finger comprises an insulating layer disposed upon the semiconductor substrate and a conductive layer disposed upon the insulating layer, and wherein each gate finger is separated from an adjacent gate finger by a conductive diffusion region in the semiconductor substrate;
- and
- ion-implanted tips extending each diffusion region under adjacent gate fingers, wherein a pair of ion-implanted tips under each gate finger comprises a continuous conductive region under the gate finger.
A method, comprising:
- forming a plurality of gate fingers on a semiconductor substrate, wherein each gate finger comprises an insulating layer disposed upon the semiconductor substrate and a conductive layer disposed upon the insulating layer;
- diffusing conductive regions between pairs of gate fingers;
- and
- extending the conductive regions under the gate fingers with ion-implanted tips, wherein a pair of ion-implanted tips under each gate finger comprises a continuous conductive region under each gate finger.
1 more element
A device, comprising:
- a self-aligning gate structure disposed upon a semiconductor substrate, the self-aligning gate structure comprising a mesh having an array of openings to the semiconductor substrate, the self-aligning gate structure further comprising an insulating oxide layer disposed upon the semiconductor substrate and a conductive layer disposed upon the insulating layer;
- conductive diffusion regions in the semiconductor substrate, wherein the diffusion regions are bounded by the openings to the semiconductor substrate;
- and
- ion-implanted extensions of the diffusion regions under the self-aligning gate structure in two different dimensions, wherein adjacent diffusion regions are connected by conductive bridges under the insulating layer.
1 more element
A method, comprising:
- forming a self-aligning gate structure on a semiconductor substrate, the self-aligning gate structure comprising a mesh having an array of openings to the semiconductor substrate, the self-aligning gate structure further comprising an insulating oxide layer disposed upon the semiconductor substrate and a conductive layer disposed upon the insulating layer;
- diffusing conductive regions in the semiconductor substrate, wherein the diffusion regions are bounded by the openings to the semiconductor substrate;
- and
- extending ion-implanted tips from the diffusion regions under the self-aligning gate structure in two different dimensions, wherein adjacent diffusion regions are connected by conductive bridges under the insulating layer.
1 more element
An apparatus, comprising:
- means for increasing the capacitance per unit area of an MOS capacitor;
- and
- means for coupling the MOS capacitor to an MOS tunnel diode to form a floating gate memory device.
Dependencies are inferred from the claim text.