US 2008/0288805 A1 · SYNCHRONIZATION DEVICE AND METHODS THEREOF

Abstract

A device includes different clock domains. Each clock domain is synchronized to a different clock signal, and the data transfer between clock domains occurs through a FIFO memory. It is determined which clock domain has a slower clock frequency, and the clock domain associated with the slower clock is selected to generate pointers used to access the FIFO memory in both clock domains. Therefore, the pointers are used to read and write data at the FIFO memory resulting in a transfer of the data between the clock domains. Because the pointers used for data transfer are generated and provided by the clock domain associated with the slower clock, the latency resulting from transferring the pointer between the clock domains is reduced.

Claims22

Dependent claims

A method, comprising

receiving a first clock signal at a first synchronous logic module of a device;
receiving a second clock signal at a second synchronous logic module of a device, the second clock signal asynchronous with the first clock signal;
determining that a frequency of the second clock signal is greater than a frequency of the first clock signal;
and
providing a first pointer from the first synchronous logic module to the second synchronous logic module in response to determining that the frequency of the second clock signal is greater than the frequency of the first clock signal, the first pointer associated with a first location of a first FIFO memory.

2 more elements

Dependencies are inferred from the claim text.

Synchronization device and methods thereof

Life of this patent

Synchronization device and methods thereof

Life of this patent

Abstract

Claims22