Dynamic core switching

A device comprising:

• memory that stores an operating system (OS) including a kernel that provides services to applications;
• and
• a core switching module that switches operation between a first mode and a second mode, wherein during said first mode, instructions associated with said applications are executed by a first asymmetric core, and a second asymmetric core is inactive, and wherein during said second mode, said instructions are executed by said second asymmetric core, and said first asymmetric core is inactive, and
• wherein said core switching module operates at a level above said kernel.

A method comprising:

• executing instructions associated with applications using a first asymmetric core when a second asymmetric core is inactive during a first mode;
• executing said instructions using said second asymmetric core when said first asymmetric core is inactive during a second mode;
• receiving a switch signal to switch operation between said first mode and said second mode;
• disabling interrupts during said first mode based on said switch signal;
• stopping processing of said applications by said first asymmetric core after said interrupts are disabled;
• transferring a state of said first asymmetric core to said second asymmetric core;
• allowing said second asymmetric core to resume execution of said instructions;
• and
• enabling said interrupts.

A method comprising:

• storing an operating system (OS) including a kernel that provides services to applications;
• executing instructions associated with said applications using a first asymmetric core when a second asymmetric core is inactive during a first mode;
• executing said instructions using said second asymmetric core when said first asymmetric core is inactive during a second mode;
• switching operation between said first mode and said second mode using a core switching module;
• and
• executing said core switching module at a level above said kernel.

A core switching system, comprising:

• mode switching means for switching operating modes, wherein said mode switching means receives a switch signal to switch between a first mode and a second mode,
• wherein during said first mode, instructions associated with applications are executed by first asymmetric core means for executing said instructions, and second asymmetric core means for executing said instructions is inactive,
• wherein during said second mode, said instructions are executed by said second asymmetric core means, and said first asymmetric core means is inactive;
• core activation means for activating said first and second asymmetric core means, wherein said core activation means stops processing of said applications by said first asymmetric core means after interrupts are disabled;
• and
• state transfer means for transferring a state of said first asymmetric core means to said second asymmetric core means,
• wherein said core activation means allows said second asymmetric core means to resume execution of said instructions and said interrupts are enabled.

A device comprising:

• memory that stores an operating system (OS) including a kernel that provides services to applications;
• and
• core switching means for switching operation between a first mode and a second mode, wherein during said first mode, instructions associated with said applications are executed by first asymmetric core means for executing said applications, and second asymmetric core means for executing said applications is inactive, and wherein during said second mode, said instructions are executed by said second asymmetric core means, and said first asymmetric core means is inactive, and
• wherein said core switching means operates at a level above said kernel.

A computer program stored on a computer readable medium and executed by a processor, comprising:

• executing instructions associated with applications using a first asymmetric core when a second asymmetric core is inactive during a first mode;
• executing said instructions using said second asymmetric core when said first asymmetric core is inactive during a second mode;
• receiving a switch signal to switch operation between said first mode and said second mode;
• disabling interrupts during said first mode based on said switch signal;
• stopping processing of said applications by said first asymmetric core after said interrupts are disabled;
• transferring a state of said first asymmetric core to said second asymmetric core;
• allowing said second asymmetric core to resume execution of said instructions;
• and
• enabling said interrupts.

A computer program stored on a computer readable medium and executed by a processor, comprising:

• storing an operating system (OS) including a kernel that provides services to applications;
• executing instructions associated with said applications using a first asymmetric core when a second asymmetric core is inactive during a first mode;
• executing said instructions using said second asymmetric core when said first asymmetric core is inactive during a second mode;
• switching operation between said first mode and said second mode using a core switching module;
• and
• executing said core switching module at a level above said kernel.