US 2008/0288730 A1 · Transactional Memory System Which Employs Thread Assists Using Address History Tables

Abstract

A computing system uses specialized “Set Associative Transaction Tables” and additional “Summary Transaction Tables” to speed the processing of common transactional memory conflict cases and those which employ assist threads using an Address History Table and processes memory transactions with a Transaction Table in memory for parallel processing of multiple threads of execution by support of which an application need not be aware. Special instructions may mark the boundaries of a transaction and identify memory locations applicable to a transaction. A ‘private to transaction’ (PTRAN) tag, directly addressable as part of the main data storage memory location, enables a quick detection of potential conflicts with other transactions that are concurrently executing on another thread of said computing system. The tag indicates whether (or not) a data entry in memory is part of a speculative memory state of an uncommitted transaction that is currently active in the system.

Claims24

Dependent claims

A multithreaded microprocessor comprising:

a microprocessor having a plurality of cores for supporting a plurality of threads for supporting transactional memory operations,
a storage element for storing an address history table (AHT) having entries for a storage access written in said AHT by load store units of said microprocessor,
a plurality of interfaces for command and control and a general purpose register coupled to an interface for copying and moving entries in said AHT.

A method for use by a transaction program on a computing system for managing memory access to a shared memory location for transaction data of a first thread, the shared memory location being accessible by the first thread and a second thread, the method comprising:

providing an assist thread to parallelize the execution of a transaction of said transaction data of said first thread to allow said first thread of execution to continue to a next instruction while utilizing a data buffer for communication between the first thread of execution and the assist thread,
executing a string of instructions to complete a transaction of said first thread, beginning with one instruction of said string of instructions, and
determining whether said one instruction is part of an active atomic instruction group (AIG) of instructions associated with said transaction of said first thread,
if said one instruction is part of an active AIG, locating a transaction table which provides for entries in an active mode for said AIG wherein all storage locations inspected or modified by instructions of said active AIG remain pending until the computing system indicates that the storage locations should be committed, and
if said one instruction is not part of an active AIG, then executing a next instruction under normal execution mode.

2 more elements

A method for use by a transaction program on a computing system having a plurality of microprocessors for managing memory access to a shared memory location for transaction data of a first thread, the shared memory location being accessible by the first thread and a second thread, the method comprising:

providing n assist threads numbering from 1 to n, the number of which assist threads can be different than the number of microprocessors, to parallelize the execution of a transaction of said transaction data of said first thread to allow said first thread of execution to continue to a next instruction while utilizing a data buffer for communication between the first thread of execution and the assist thread, and
executing a string of instructions with said microprocessors to complete a transaction of said first thread, beginning with one instruction of said string of instructions.

Dependencies are inferred from the claim text.

Transactional Memory System Which Employs Thread Assists Using Address History Tables

Life of this patent

Transactional Memory System Which Employs Thread Assists Using Address History Tables

Life of this patent

Abstract

Claims24