Bus system and method of arbitrating the same

A display system comprising:

• a bus;
• a device that displays data received from the bus;
• at least one bus master device that generates a burst cycle control signal, a transfer start signal and a bus control request signal for requesting control of the bus, and is activated in response to a bus control grant signal, so as to exchange data via the bus;
• a bus arbiter that generates the bus control grant signal in response to the bus control request signal and provides the bus control grant signal to the at least one bus master device;
• and
• at least one transfer mode selection circuit that converts an operation mode of the at least one bus master device from a burst mode to a single mode to generate a selection signal, when the bus control grant signal is deactivated before a burst mode operation is completed.

A multi-core processor system comprising:

• a bus;
• a plurality of bus master devices that respectively generate burst cycle control signals, transfer start signals and bus control request signals for requesting control of the bus, and respectively are activated in response to a corresponding bus control grant signal, so as to respectively exchange data via the bus;
• a bus arbiter that generates the bus control grant signal in response to the bus control request signals and provides the bus control grant signal to one of the plurality of bus master devices;
• and
• a plurality of transfer mode selection circuits that respectively convert an operation mode of the corresponding bus master device from a burst mode to a single mode to generate a selection signal, when the bus control grant signal is deactivated before a burst mode operation is completed.