System and method of determining the speed of digital application specific integrated circuits

A system for identifying a running speed of an integrated circuit, comprising:

• at least first and second asynchronous multi-rail circuits configured to receive input data and transmit output data;
• at least first and second completion detection circuits configured to generate at least first and second completion detection signals for said at least first and second asynchronous circuits, respectively;
• at least first and second variable clock generators configured to be driven by at least said at least first and second completion detection signals, respectively;
• a synchronous circuit element configured to receive at least a portion of said output data and configured to be clock driven by a clock signal from at least one said first and second variable clock generators;
• wherein said at least first and second variable clock generators will self-adjust toward a universal clock speed that represents a running speed of said asynchronous circuit.