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US 2008/0259703 A1Published application
Self-timed synchronous memory
AssigneeCypress Semiconductor Corporation
InventorOnur Ozbek
Life of this patent
Estimating the term…
Abstract
A memory device includes a memory array having a plurality of memory cells arranged in a row-column format, where the memory array is configured to designate at least one of the memory cells as a test memory cell. The memory system also includes a sense amplifier to read the test memory cell and to evaluate a validity of the memory array responsive to reading the test memory cell.
Claims20
A device comprising:
- a memory array including a plurality of memory cells arranged in a row-column format, where the memory array is configured to designate at least one of the memory cells as a test memory cell;
- and
- a sense amplifier to read the test memory cell and to evaluate a validity of the memory array responsive to reading the test memory cell.
A method comprising:
- reading a test memory cell in a memory array, the memory array having a plurality of memory cells arranged in a row-column format and configured to designate at least one of the memory cells as the test memory cell;
- and
- evaluating a validity of all of the memory cells in the memory array responsive to the reading the test memory cell.
A system comprising:
- structure for reading a test memory cell in a memory array, the memory array having a plurality of memory cells arranged in a row-column format and configured to designate at least one of the memory cells as the test memory cell;
- and
- structure for evaluating a validity of all of the memory cells in the memory array responsive to the reading the test memory cell.
Dependencies are inferred from the claim text.