Semiconductor Device

A semiconductor device including a semiconductor memory, wherein the semiconductor memory comprises:

• a data input output buffer to send the input data from an external data bus to an internal input data bus, and to send the output data from an internal output data bus to the external data bus,
• the first data bus and the second data bus,
• the first select circuit to select one of the first data bus or the second data bus, and to output to the internal data bus,
• an address bus to include a row address bit and a memory bank address bit,
• the first memory device including the number of the memory banks indicated by the memory bank address bit, including the plurality of rows indicated by the row address bit and the first number of the row data for each of the plurality of rows, to input the data from the first data bus, and to output the data to the second data bus,
• the third memory device including the number of the cache data banks indicated by the second data number including the plurality of rows and the number of row data indicated by the first number, to output the data to the first data bus, and to input the data from the second data bus,
• the fourth memory device including the number of cache tag banks indicated by the second number including the plurality of rows, to input to data from the memory bank address bit of the address bus, and
• the control circuit including the function of determining a cache hit or a cache miss by comparing the data read from the fourth memory device with the memory bank address bit of the address bus, when the data write instruction or the data read instruction is issued to the semiconductor memory, to control the first, the third, and the fourth memory devices,
• wherein, if the write cycle time of the first device is N (N≧2) times as long as that of the read cycle time, the second number is equal to or larger than N with the semiconductor device.