Nonvolatile semiconductor memory device

A nonvolatile semiconductor device comprising:

• a plurality of word lines;
• a plurality of bit lines;
• a plurality of memory cell arrays having a plurality of electrically reprogrammable memory cells which are connected to said word lines and said bit lines;
• a data program control section which programs a plurality of first multi-bits data each having a first number of bits, or a plurality of second multi-bits data each having a second number of bits twice that of said first multi-bits data, to said plurality of memory cell arrays;
• a page buffer circuit which stores said plurality of first multi-bits data or said plurality of second multi-bits data which is read for each of said word lines from said plurality of memory cell arrays;
• a sense amplifier section which stores said plurality of first multi-bits data or said plurality of second multi-bits data which is read for each of said second number of bits from said page buffer circuit synchronized with a second clock signal having a cycle which is twice that of a first clock signal;
• a data transfer control circuit which transfers said data which is stored in said sense amplifier section which is read for each of said second number of bits synchronized with a second clock signal;
• and
• a data output section which receives said data from said data transfer control circuit and outputs externally said data in synchronization with said first clock signal.

A method of data transfer in a nonvolatile semiconductor memory device comprising:

• reading a plurality of first multi-bits data each having a first number of bits or reading a plurality of second multi-bits data each having a second number of bits twice that of said first multi-bits data, for each of said second number of bits from a page buffer circuit synchronized with a first clock signal which is synchronized with a second clock signal having a cycle twice that of said first clock signal, said data being read for each word line from a plurality of memory cell arrays and stored in said page buffer circuit;
• transferring said data which is read from said page buffer circuit to a plurality of registers arranged in said second number of bits and storing said data in said plurality of registers;
• and
• transferring said data which is stored in said plurality of registers externally from said plurality of registers synchronized with said first clock signal for each volume of data of said first number of bits.