Analog level shifter
AssigneeMediatek Inc.
InventorsChih-Chien Huang, Wei-Liang Lee
Life of this patent
Estimating the term…
Abstract
An analog level shifter is provided, receiving an input voltage to generate an output voltage. In the analog level shifter, a NMOS transistor has a gate coupled to an input node where the input voltage is input. A resistance device comprises a first end coupled to source of the NMOS transistor, and a second end coupled to an output node where the output voltage is output. A current source is coupled to the output node, sinking a first current therefrom to ground.
Claims13
An analog level shifter, receiving an input voltage to generate an output voltage, comprising:
- an NMOS transistor with a gate coupled to an input node where the input voltage is input;
- a resistance device comprising a first end coupled to a source of the NMOS transistor, and a second end coupled to an output node where the output voltage is output;
- and
- a current source coupled to the output node, sinking a current therefrom;
- wherein the resistance device is a P-poly, N-poly, or diffusion type resistor.
(canceled)
An analog level shifter, receiving an input voltage to generate an output voltage, the analog level shifter comprising:
- a PMOS transistor with a gate coupled to an input node where the input voltage is input;
- a resistance device comprising a first end coupled to a source of the PMOS transistor, and a second end coupled to an output node where the output voltage is output;
- and
- a current source coupled to the output node, the current source providing a current to the resistance device:
- wherein the resistance device is a P-poly, N-poly, or diffusion type resistor.
(canceled)
Dependencies are inferred from the claim text.