US 2008/0258796 A1Published application

Circuit arrangement and method for limiting a signal voltage

AssigneeNational Semiconductor Germany AG

InventorERNESTO ROMANI

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Abstract

The present invention relates to the field of signal processing. It is an object of the invention to provide a circuit arrangement (VL) and a method for limiting a signal voltage upstream of a processing stage (A) of a signal processing device, by means of which circuit arrangement and method it becomes possible to reduce signal interference. It is provided a voltage comparison (OPAMP2) within a closed-loop control of an output signal (Vin′), by means of which closed-loop control the value of said output signal (Vin′) is limited to a maximum value (Vmax/2). Thus, it becomes possible to prevent the generation of signal interference during signal processing. The voltage limiting method according to the invention uses as a reference quantity a reference voltage (Vmax/2) to which the output signal (Vin′) is compared in the context of closed-loop control. A closed-loop control deviation signal of this closed-loop control controls the variable-resistance voltage divider component (T1) at which the output signal (Vin′) is formed, e.g. directly picked up, as a voltage drop.

Claims7

Dependent claims

A circuit arrangement for limiting a signal voltage upstream of a processing stage (A) of a signal processing device, in particular upstream of an amplifier stage of a sigma-delta analogue-digital converter, comprising:

an input for inputting an input signal (Vin),
an output for outputting an output signal (Vin′) to the processing stage (A), and
a voltage limiting circuit (VL) connected to the input and the output, to which voltage limiting circuit (VL) the input signal (Vin) is fed, and which voltage limiting circuit (VL) from this forms the output signal (Vin′) such that
in the case of the value of the input signal (Vin) being less than that of a predetermined maximum voltage (Vmax) the output signal (Vin′) is essentially proportional to the input signal (Vin), and
in the case of the value of the input signal (Vin) exceeding that of the predetermined maximum voltage (Vmax) the output signal (Vin′) is essentially constant,
wherein the voltage limiting circuit (VL) comprises:
a voltage divider (R1a, T1;
R1a, T1, R1c) to which the input signal (Vin) is applied and which comprises at least one voltage divider component (T1) whose resistance can be varied by means of a control signal, and at which voltage divider component (T1) the output signal (Vin′) is formed as a voltage drop, and
a differential amplifier (OPAMP2) for amplifying the difference between the output signal (Vin′) and a reference voltage (Vmax/2) that corresponds to the maximum voltage (Vmax), with the output signal of said differential amplifier (OPAMP2) being fed as the control signal to the variable-resistance voltage divider component (T1).

6 more elements

Dependencies are inferred from the claim text.